Apr 23, 2014
Industry’s Highest Capacity SoC Interconnect IP Core from DMP Adopted by eSilicon

Digital Media Professionals Inc.(DMP), a leading provider of 3D/2D graphics and computing intellectual property(IP) cores, announced today that eSilicon Corporation, a leading independent semiconductor design and manufacturing services provider, has adopted DMP Loputo SoC Interconnect IP. eSilicon chose DMP Loputo IP to develop and deliver next-generation SoCs.

DMP Loputo Interconnect IP supports a unique bus structure based on the concept of the multi-layer interconnection matrix with smart arbiter. DMP Loputo Interconnect IP enables SoC designers to achieve lower, smaller die size and offers the ability to reduce the number of interconnect wires to reduce routing congestion at the back-end place and route phase. DMP Loputo Interconnect IP supports various on-chip protocols such as AMBA® AXI and OCP.

Our ASICs are deployed in a wide range of applications and require superior performance, reliability, and lower SoC costs. After examining the available solutions in the industry, it was clear that DMP delivered SoC Interconnect IP that we needed, said Gino Skulick, vice president and general manager, IC Solutions at eSilicon.
DMP met our functional and performance requirements, and their reputable technology, IP development expertise and strong customer reputation make them a valued supplier.

It is quite obvious that the newest SoCs, designed for applications such as Advanced Driver Assistance System(ADAS) need real-time performance with extremely low latency between critical IP blocks such as CPU, GPU and Vision Processor. SoC Interconnect IP handles high-speed communications between each of the processors and common memory. That is the key factor influencing system performance and cost, said Tatsuo Yamamoto, CEO, DMP.
Our Loputo Interconnect is groundbreaking proprietary technology based on the accumulation of GPU expertise and highly advanced SoC development experience. It enables our customers to achieve lower power, smaller die area and easier implementation of complex SoCs.