PICA realizes a flexible, scalable, and innovative hardware architecture to meet broad demand for SoC (System on Chip) applications for the rapidly growing "21st-century Digital Consumer Market," such as amusement machines, car infotainment systems, mobile phones, game consoles, and digital appliances. In addition, DMP offers OEM chip development service based on its chip development capabilities proven in the launch of ULTRAY2000 in 2005.

The internal bus structure of PICA, which conforms with OCP (Open Core Protocol) supported by OCP-IP, assures IP interoperability and design costs and risks can be reduced. DMP's unique technology (Development Code Name: MAESTRO-2G), which can be implemented as a 3D extension module, achieves high-performance and reduces content sizes and memory bandwidth for the embedded applications. In addition, high-quality visual effects which could not be achieved in digital consumer products before can be achieved through a quick and easy programming.

The software development environment contains low-level drivers (libraries), emulators supported on PCs, and a suite of authoring support tools for the seamless workflow from major CG tools. In addition, these development tools are compliant with OpenGL ES and OpenVG, which are industry-standard APIs created by The Khronos Group, enabling reuse of existing software assets. DMP's graphics solutions including 2D/3D with solid support for hardware and software allow customers to design and develop products optimized to their applications in minimal lead time. DMP is also a member of Futuremark's Benchmark Development Program, and is participating in the development of OpenGL ES industry-standard benchmark software.

3D graphics IP core for next-generation embedded devices. Comprising a maximum of four programmable vertex processors, a maximum of four rendering pipelines, and 3D extension module (MAESTRO-2G).

A vector graphics module compliant with OpenVG. Can be used as a PICA-FBM add-on module (licenses scheduled to be granted from the end of 2006).

The number of vertex processors, the number of rendering pipelines, implementation of MAESTRO-2G optional modules, and memory configuration (external/internal) are all customizable through using building-block architecture in line with demand for target SoC functionality, performance and cost. In addition, this can also be used to flexibly respond to the unique, overall system-level integration needs of each customer, such as meeting the requirements for the target platform, including most embedded CPUs, OS, video codecs, and any semiconductor-manufacturing process.

Enables the fast execution of simple procedures to achieve realistic 3D visual effects using a variety of hardware shading and their combinations by implementing a 3D extension module (MAESTRO-2G).

PICA-FBM (image post-processing module) quickly generates high-quality images for the final output to screens, through full-scene anti-aliasing, multi-layer compositing (maximum of eight layers), a resizing function, a color and spacing conversion function, a scrolling function, etc. Furthermore, PICA-VG (vector graphics module) will enable the development of high image quality, operability, excellent 2D maps, and skin UIs, etc.

Enables the production of small-sized and reduced-memory bandwidth contents with OpenGL ES standard texture compression functionality, polygon subdivision functionality and procedural textural functionality in the 3D extension module (MAESTRO-2G), and through implementing PICA-VG.

Enables the execution of skin animation without overburdening the CPU using the programmable vertex processor (up to four). Provides solid support for increasing the speed and quality of character animation, which is becoming an important element in the amusement field.