News

Press Release: DMP adds OpenGL ES 2.0 shader-based graphics IP to its new "SMAPH" graphics IP core family

2009.11.16

“SMAPH-S” is the world’s smallest and most scalable OpenGL ES 2.0 IP core and sets a new benchmark for mobile to high performance computing devices

DMP today announced “SMAPH-S”, a next generation OpenGL ES 2.0 shader-based graphics IP core. DMP will start providing the core to initial customers in 1Q 2010.

SMAPH-S is a high-performance 3D graphics IP core that offers industry lowest power consumption with its state-of-the-art power saving technologies and highly optimized OpenGL ES 2.0 based-shader pipelines. SMAPH-S meets the widespread demand for ASIC/ASSP/SoC applications including mobile devices, consumer electronics, automotive, industry, game consoles, and entertainment devices. With its support of scalable shader architecture, the total number of the geometry and pixel processors can be configured from as small as 2 for entry level mobile devices, up to 24 for high performance devices.

SMAPH-S will be compliant with OpenGL ES 2.0 and fully supports the popular OpenGL ES 1.1, and OpenVG 1.1 standards.

SMAPH-S supports industry standard OCP and AMBA AXI bus interconnect as well as DMP’s proprietary architecture such as optimized cache structure for memory interfaces, which make it easy to integrate the IP into SoC, and achieve system level performance goals in real life implementations.

DMP continues to work with 3rd party middleware tool vendors and offers a variety of content creation tool chains to meet the wide range of needs for different types of application development.

DMP will exhibit SMAPH-S at the “Embedded Technology 2009”, one of Japan’s largest embedded technology trade shows, which will be held in Yokohama, Japan on November 18th – November 20th.

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* Company names and product names described above are either registered trademarks or trademarks of the holders.

DMP demonstrates 3D/2D graphics IP core products at ET2009 (Finished)

2009.10.15

DMP has announced its participation at the "Embedded Technology 2009", one of Japan’s largest embedded technology trade shows, which will be held in Yokohama Japan on November 18th – November 20th (booth#: B-02 ). DMP will demonstrate and present specialized solutions including new OpenGL ES 2.0 shader-based graphics IP core "SMAPH-S" and SMAPH-F (High-performance vector graphics IP core) which meet the demands of various embedded UI (User Interface) applications. Our demos illustrate several combinations of IP cores, device targets (ASIC/FPGA etc) and middleware.　

>>This exhibition has finished.

Press Release: DMP unveils "PICA200 for FPGA " – Industry’s first FPGA based full 3D graphics IP solution-

2009.05.11

Digital Media Professionals Inc. (DMP hereafter), the world-class leader of 3D graphics solutions headquartered in Tokyo Japan today announced the “PICA200 for FPGA” a 3D Graphics IP core developed for embedded products shipped with FPGAs. PICA200 for FPGA is based on the OpenGL ES compliant popular PICA200 3D graphics IP, which has already been employed in many embedded and consumer electronics products.

PICA200 for FPGA has been specifically developed for customers who need full 3D graphics capability on FPGA based products, and to accommodate unique requirements such as long-term supply and/or small size production volume, which standard off-the-shelf GPU or expensive ASIC development processes have not fulfilled. PICA200 for FPGA, with its small core size and high performance already proven on the popular PICA200 graphics IP, fits a wide range of embedded applications including industrial, medical, aerospace, safety-critical, and semiconductor equipments. PICA200 for FPGA supports XGA (1024 x 768) screen resolution and provides more than 3 million vertices at 50MHz and 1 pixel per clock performance. It’s authoring environment is based on the industry’s popular CG authoring tools such as Autodesk® Maya® and 3ds Max® and provides a seamless, highly effective, and low cost content production process.

PICA200 for FPGA is available for licensing now and the first customer product based on it will be shipped in 2H 2009. The lead-off FPGA supported by PICA200 for FPGA is Xilinx®Virtex®-5 FPGA.

“PICA200 for FPGA meets the demands of today’s complex and advanced graphics applications on FPGA based embedded products.” said Shinichi Shiratsuchi, Deputy Director Marketing Department, Xilinx K.K. ” DMP fully exploited the built-in performance and power saving features of industry leading Virtex-5 FPGA and provided break-though 3D graphics capability without sacrificing the flexibility in production and development. “

It is now on the menu to be followed by Altera Stratix® III and other FPGA platforms.

“Altera welcomes PICA200 for FPGA to support our Stratix® FPGA family”, said Nobuo Horiuchi, Director, Japan Marketing, Altera Japan Ltd. “Altera’s Stratix Family and DMP’s graphics solutions for FPGA allow development of highly sophisticated graphics application with advanced design flexibility and will expand the FPGA market much further.”

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* Company names and product names described above are either registered trademarks or trademarks of the holders.

Press Release: DMP announces new vector graphics core "SMAPH-F" – Industry’s Highest Performance Vector Graphics IP -

2009.04.23

Digital Media Professionals Inc. (DMP hereafter), the world-class leader of 3D graphics solutions, headquartered in Tokyo Japan today announced the “SMAPH-F”, a next generation vector graphics IP core. DMP will make the core available to customers in 3Q 2009. The core has already been licensed to a major Japanese Tier-1 automotive supplier. DMP will exhibit the SMAPH-F at the “ESEC 2009” (booth#: E38-1 )., one of Japan’s largest embedded technology trade shows, which will be held in Tokyo Japan on May 13th – May 15th.

SMAPH-F enables the industry’s most advanced GUI applications for entry level embedded products such as mobile, TVs, digital cameras, graphics meters, navigation, gaming, office products, etc. at very low cost and low power consumption, while achieving the industry’s best vector graphics performance. SMAPH-F will be compliant with Khronos Group OpenVG 1.1 and provides highly efficient acceleration of vector graphics contents including Adobe® Flash Lite® and SVG. SMAPH-F also supports “DMP Gradient Extension”, a built-in unique hardware acceleration of gradient animations, and additional procedural texturing such as woody pattern. DMP Gradient Extension is provided as an optional feature.

With its support of industry standard OCP and AXI bus interconnect as well as DMP’s state of the art design for optimum system performance with DDR burst accesses, SMAPH-F is a very friendly IP in terms of integration and achievement of performance goals in SoCs which are becoming increasingly complex today.

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* Company names and product names described above are either registered trademarks or trademarks of the holders.

DMP at ESEC 2009 (Finished)

2009.03.26

DMP has announced its participation at the "ESEC 2009", one of Japan’s largest embedded technology trade shows, which will be held in Tokyo Japan on May 13th – May 15th (booth#: E38-1 ). DMP will demonstrate and present new graphics IP core products that cover a wide area of applications ranging from high-performance amusement systems to low-power mobile applications.

>>This exhibition has finished.

Press Release: DMP, Acrodea in joint marketing drive for innovative UI solutions

2009.02.13

DMP and Acrodea, Inc. announced an agreement to conduct joint marketing for the development of innovative user interfaces employing DMP’s PICA graphics IP core and Acrodea’s VIVID UI technology targeting digital consumer electronics market.

 * Company names and product names described above are either registered trademarks or trademarks of the holders.

Nifco Advanced Technology licensed DMP’s PICA200 for use in "NV7" GPU

2008.04.23

DMP reports that Nifco Advanced Technology Inc., a leading fabless semiconductor company, has selected DMP’s PICA200 graphics core for use in "NV7" GPU targeting amusement market.

DMP announces two day Getting Start GLSL Programming training course

2007.06.25

DMP announced a two day getting start GLSL Programming training course. The OpenGL ES roadmap has been tailored to the diverse needs of the embedded industry and contains two tracks with “1.X” and “2.X” specification roadmaps that will evolve in parallel. The 1.X roadmap will continue to be developed for new-generation fixed function 3D accelerators while the 2.X roadmap will enable emerging programmable 3D pipelines.This course introduce the world of programmable pipeline by explaining basic topics of the GLSL(OpenGL Shading Language) which is a core feature of OpenGL ES 2.x and OpenGL 2.x.
(* This course is held in Japanese )

DMP’s "PICA" won the Excellent IP Prize of 9th LSI IP Design Award

2007.05.11

DMP’s "PICA" 3D graphics IP core won the Excellent IP Prize which is the best prize of 9th LSI IP Dsign Award. The LSI Design Award Committee* evaluated not only high-speed and the high-quality drawing performance of PICA but also practicality, and reliability of PICA as hardware IP product.
( *constituted by Matsushita Electric Industrial Co., Ltd., NEC Electronics Corp., Toshiba Corp., Renesas Technology Corp., Fujitsu Ltd., Rohm Co., Ltd., Seiko Epson Corp., Meitec Corp., IPTC, Development Bank of Japan, and Nikkei Business Publications, Inc.)

DMP announces Advanced OpenGL ES Programming training course

2007.03.02

DMP announced one day of Advanced OpenGL ES Programming Training in Tokyo. This course demonstrates the more sophisticated techniques possible using the OpenGL ES 1.1. By explaining the techniques required to generate images of greater realism, the course provides deeper insights into OpenGL ES functionality. Also, this course refer to performance aspects of OpenGL ES application and basic concept of OpenGL ES 2.x. Participants must have programming knowledge (especially C), a good grasp of computer graphics concepts as well as a familiarity with the basic topics of the OpenGL ES 1.1.
( *This course is held in Japanese.)