Press Releases
Press Releases
DMP Introduces High-End OpenGL ES 2.0 IP Cores and Multi-Core Configurations to Its SMAPH-S Product Family
2012.05.07
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Contact: Petri Talala Digital Media Professionals USA Inc. Phone: +1-408-807-2600 Email: infous11@dmprof.com |
DMP Introduces High-End OpenGL ES 2.0 IP Cores and Multi-Core Configurations to Its SMAPH-S Product Family
Company also extends its low-end offering with the world’s smallest OpenGL ES 2.0 IP core: SMAPH-S Lite
Tokyo, Japan– May 7th, 2012 – Digital Media Professionals Inc. (DMP), a leading provider of 2D/3D graphics Intellectual Property (IP) cores, today ann1ounced significant product expansion to its scalable SMAPH-S shader based Graphics IP Core product family including:
- New high-end and OpenGL ES 2.0 compliant IP cores with multi core deployment (MP) support that offers the industry leading graphics rendering and computing performance.
- SMAPH-S Lite, the most cost effective graphics IP core that offers the smallest OpenGL ES 2.0 compliant silicon footprint in the industry.
All new SMAPH-S IP cores are ready for customers’ SoC deployments immediately.
DMP’s SMAPH-S OpenGL ES 2.0 product family offers the industry’s best scalability from low-end graphics cores to high-end. When SMAPH-S Lite is the smallest OpenGL ES 2.0 IP core in the world, the new high-end SMAPH-S variants and multicore configurations will provide the highest performance in the market, but also 2-4 times smaller die size and power consumption compared to competitive offerings today. This IP product offering has been achieved by DMP’s innovative and state-of-the-art SMAPH-S architecture design where it is easy to increase or decrease the number of shader processors and/or rendering pipelines to meet exact performance, die size, and power consumption requirements of the target platform. The highlights for new SMAPH-S high-end IP cores are:
- Number of shader processors (SP) is extended to 32 at each core.
- Number of rendering pipelines is extended to 4 at each core.
- Multi core configuration is supported up to 4MPs.
SMAPH-S Lite is a tiny 3D graphics IP core that offers industry lowest power consumption based on its innovative power saving technologies and highly optimized OpenGL ES 2.0 based shader pipelines. SMAPH-S Lite has been optimized to offer ultra-low power, good performance and low cost GPU solution to modern applications in a wide range of consumer devices starting from entry-level feature mobile phones, to other consumer devices such as printers and cameras.
“Our customers are demanding embedded graphics solutions that meet extremely low-cost, low-power requirements and can still deliver good performance and visually pleasing user interfaces in consumer devices. Same time mobile and tablet industry is looking for ultra-high resolutions to be supported in next generation mobile devices and this will require high-end and multicore graphics offering to fill this significantly increased pixel pipeline” said Tatsuo Yamamoto, CEO of DMP. “By scaling our SMAPH-S graphics cores to low and high ends we answer our customers’ needs and further strengthen our industry leadership to provide the most scalable graphics IP offering with the highest performance and the best power efficiency per square millimeter of silicon area.”
DMP will demonstrate new SMAPH-S IP core family at Japan’s embedded tradeshows “ESEC 2012,Tokyo” on May 9th –11th, and at “COMPUTEX TAIPEI 2012” on June 5th – 9th, the largest computer exhibition in Asia.
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About DMP
Digital Media Professionals Inc. (DMP)(TOKYO:3652) develops industry leading 2D/3D graphics solutions to global consumer electronics, mobile, embedded and automotive markets. Company has been founded at Tokyo, Japan in 2002 and is currently developing several graphics IP cores based on the open Khronos™ Group standards and DMP’s cutting edge 3D graphics technology DMP Maestro Technology.
For more about DMP, please visit our website: http://www.dmprof.com/english/
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DMP Joins TSMC Soft IP Alliance
2011.10.11
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PR Contact: Keisuke Kirii IR Contact: Hiroyuki Ito Phone: +81-422-60-3480 Email: info_06@dmprof.com |
Digital Media Professionals(DMP) Joins TSMC Soft IP Alliance
Tokyo, Japan – October 11th, 2011 – Digital Media Professional Inc. (DMP)(TOKYO:3652), a leading provider of 2D/3D graphics IP core, today announced that it has joined the TSMC Soft IP Alliance Program.
DMP graphics IP cores feature low-power, small footprint and high performance for embedded graphics applications in mobile, home, car, amusement and office.
“We’re pleased to join TSMC’s Soft IP Alliance Program to help accelerate our business both here and abroad,” said Tatsuo Yamamoto, President & CEO of DMP.
“Adding DMP gives our customers greater access to their products and enhances customers’ confidence in the quality of result via our IP assurance program,” said Suk Lee, TSMC Director of Design Infrastructure Marketing.
About DMP
Digital Media Professionals Inc. (DMP)(TOKYO:3652) is a world-class leader bringing 2D and 3D graphics solutions to market from Japan since its founding in 2002, and is currently developing graphics IP core based on DMP’s cutting edge 3D graphics technology DMP Maestro Technology.
Head office: 1-15-5 Naka-cho, Musashino-shi, Tokyo, Japan
President & CEO: Tatsuo Yamamoto
For more about DMP, please visit our website: http://www.dmprof.com/english/
©2011 Digital Media Professionals Inc.
The company logo and DMP are registered trademarks or trademarks of Digital Media Professionals Inc.. Rights to other registered trademarks or other trademarks belong to their respective.
>>DMP will exhibit at TSMC’s Open Innovation Platform Ecosystem Forum
DMP and Xilinx Collaborate on Xilinx Alliance Program
2010.11.01
Press Release
DMP and Xilinx Collaborate on Xilinx Alliance Program
Tokyo, Japan November 1st, 2010 - Digital Media Professionals Inc. (DMP hereafter), a world-class leader in 2D/3D graphics solutions, headquartered in Tokyo Japan, today announced that DMP has become a member of the Xilinx, Inc. (Nasdaq: XLNX) Alliance Program.
Xilinx Alliance Program members make up a worldwide ecosystem of qualified companies that have a proven track record in delivering products and services built for Xilinx programmable logic technologies. DMP provide the competitive FPGA (Field-Programmable Gate Array) solutions in aspects of system cost benefits and lowering design risks with its IP products tightly cooperating with Xilinx’s platforms.
Through the alliance program, DMP provides the“PICA®200 for FPGA” a full 3D graphics IP core compliant with OpenGL ES 1.1 under a common set of terms known as the SignOnce IP License. DMP also provides “SMAPH®-F” a full vector graphics IP core compliant with OpenVG 1.1 to Xilinx platforms.
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About DMP
Digital Media Professionals Inc. (DMP) is a world-class leader bringing 2D and 3D graphics solutions to market from Japan since its founding in 2002, and is currently developing graphics IP core based on DMP’s cutting edge 3D graphics technology DMP Maestro Technology. (Headquarters at: 1-15-5 Naka-cho, Musashino-shi, Tokyo; Capital: 350 million JPY; President & C.E.O.: Tatsuo Yamamoto; http://www.dmprof.com/english/ )
About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit http://www.xilinx.com/.
©2010 Digital Media Professionals Inc.
The company logo, DMP, PICA, and SMAPH are registered trademarks or trademarks of Digital Media Professionals Inc. in Japan. Rights to other registered trademarks or other trademarks belong to their respective owners.
DMP Releases Android™ OpenGL ES 3D Graphics E-learning Kit
2010.07.26
Digital Media Professionals Inc. (DMP) today announced that it will start selling the English version of its Android 3D Graphics Learning Kit from August 2010. DMP will showcase the first public exhibition of its Android 3D Graphics Learning Kit (English Version) at SIGGRAPH 2010, the world’s largest computer graphics conference and tradeshow in Los Angeles, United States (Khronos Booth #1201). The kit has already been available in Japanese since February this year but the English version will allow programmers in all countries to study OpenGL ES on self learning basis.
The Android 3D Graphics Learning Kit is an e-learning aid designed to help individuals to learn programming using OpenGL ES, a standard 3D graphics API used on wide variety of embedded products today. Starting from the basics, the kit is designed to make learning programming easy, even for beginners. It enables the user to acquire the basic skills required to develop actual software by learning OpenGL ES programming through exercises performed on the Android platform.
DMP regularly conducts OpenGL ES program training courses I and II, which are approved by the Khronos Group as their official training courses, in Japan.
<Product Overview>
Product name: OpenGL ES Learning Kit for Android
Price: USD $98 (Personal License） / USD $49 (Academic License)
License period: 1 year
Number of pages: 231
Runtime: Approx. 4 hours
Press Release: DMP 3D Graphics IP core “PICA200″ is adopted by Nintendo 3DS™
2010.06.21
Digital Media professionals Inc. (HQ: Musashino-shi, Tokyo, CEO: Tatsuo Yamamoto, hereafter DMP) has announced that the DMP 3D Graphics IP “PICA200″ is adopted by Nintendo’s new portable game machine “Nintendo 3DS”.
PICA200 features proprietary DMP 3D graphics extensions “Maestro technology”. By hardware implementation of complex shader functionality, these extensions allow the high performance graphics rendering found on existing high-end products to be realized on mobile devices with low power consumption requirements, such as portable game machines.
“We had a very ambitious goal in the realization of naked-eye 3D stereo vision, and video game console style high quality graphics rendering, whilst maintaining low power consumption. I am delighted that we were able to contribute with ‘Maestro technology’, which we have developed over several years at DMP”, said Tatsuo Yamamoto, President and CEO, DMP.
* This press release is translated from original Japanese.
DMP Licenses SMAPH-F IP Cores to Renesas Electronics Corporation
2010.04.01
DMP today announced that DMP has licensed the SMAPH-F, the latest OpenVG1.1 compliant graphics IP core to Renesas Electronics Corporation, for use in its next-generation system-on-chip (SoC) for consumer applications.
MIPS Technologies and DMP Collaborate on Android™ Development for MIPS® Architecture
2010.03.17
DMP Brings New 2D/3D Hardware Graphics Acceleration Technology
to MIPS-Based™ Devices Running Android™
MIPS Technologies, Inc. and Digital Media Professionals Inc. (DMP) today announced that DMP has become a member of the MIPS Alliance Program for its Android on MIPS initiative. The alliance will ultimately enable SoC developers to create MIPS-Based SoCs with DMP PICA/SMAPH series graphics IP cores.
DMP’s OpenGL ES and OpenVG graphics IP cores including its PICA/SMAPH series cores are developed for high performance and low power embedded applications, fulfilling the increasing need for visually-rich user interfaces in products running Android. MIPS Technologies and DMP are initially working together to develop a reference platform based on a MIPS32® Malta™ development board and a DMP PICA200 3D graphics IP-based GPU (NV7). The companies plan to display the jointly-developed platform at the Embedded Systems Conference in Tokyo, May 12 – 14, 2010.
Press Release: DMP adds OpenGL ES 2.0 shader-based graphics IP to its new "SMAPH" graphics IP core family
2009.11.16
“SMAPH-S” is the world’s smallest and most scalable OpenGL ES 2.0 IP core and sets a new benchmark for mobile to high performance computing devices
DMP today announced “SMAPH-S”, a next generation OpenGL ES 2.0 shader-based graphics IP core. DMP will start providing the core to initial customers in 1Q 2010.
SMAPH-S is a high-performance 3D graphics IP core that offers industry lowest power consumption with its state-of-the-art power saving technologies and highly optimized OpenGL ES 2.0 based-shader pipelines. SMAPH-S meets the widespread demand for ASIC/ASSP/SoC applications including mobile devices, consumer electronics, automotive, industry, game consoles, and entertainment devices. With its support of scalable shader architecture, the total number of the geometry and pixel processors can be configured from as small as 2 for entry level mobile devices, up to 24 for high performance devices.
SMAPH-S will be compliant with OpenGL ES 2.0 and fully supports the popular OpenGL ES 1.1, and OpenVG 1.1 standards.
SMAPH-S supports industry standard OCP and AMBA AXI bus interconnect as well as DMP’s proprietary architecture such as optimized cache structure for memory interfaces, which make it easy to integrate the IP into SoC, and achieve system level performance goals in real life implementations.
DMP continues to work with 3rd party middleware tool vendors and offers a variety of content creation tool chains to meet the wide range of needs for different types of application development.
DMP will exhibit SMAPH-S at the “Embedded Technology 2009”, one of Japan’s largest embedded technology trade shows, which will be held in Yokohama, Japan on November 18th – November 20th.
* Company names and product names described above are either registered trademarks or trademarks of the holders.
Press Release: DMP unveils "PICA200 for FPGA " – Industry’s first FPGA based full 3D graphics IP solution-
2009.05.11
Digital Media Professionals Inc. (DMP hereafter), the world-class leader of 3D graphics solutions headquartered in Tokyo Japan today announced the “PICA200 for FPGA” a 3D Graphics IP core developed for embedded products shipped with FPGAs. PICA200 for FPGA is based on the OpenGL ES compliant popular PICA200 3D graphics IP, which has already been employed in many embedded and consumer electronics products.
PICA200 for FPGA has been specifically developed for customers who need full 3D graphics capability on FPGA based products, and to accommodate unique requirements such as long-term supply and/or small size production volume, which standard off-the-shelf GPU or expensive ASIC development processes have not fulfilled. PICA200 for FPGA, with its small core size and high performance already proven on the popular PICA200 graphics IP, fits a wide range of embedded applications including industrial, medical, aerospace, safety-critical, and semiconductor equipments. PICA200 for FPGA supports XGA (1024 x 768) screen resolution and provides more than 3 million vertices at 50MHz and 1 pixel per clock performance. It’s authoring environment is based on the industry’s popular CG authoring tools such as Autodesk® Maya® and 3ds Max® and provides a seamless, highly effective, and low cost content production process.
PICA200 for FPGA is available for licensing now and the first customer product based on it will be shipped in 2H 2009. The lead-off FPGA supported by PICA200 for FPGA is Xilinx®Virtex®-5 FPGA.
“PICA200 for FPGA meets the demands of today’s complex and advanced graphics applications on FPGA based embedded products.” said Shinichi Shiratsuchi, Deputy Director Marketing Department, Xilinx K.K. ” DMP fully exploited the built-in performance and power saving features of industry leading Virtex-5 FPGA and provided break-though 3D graphics capability without sacrificing the flexibility in production and development. “
It is now on the menu to be followed by Altera Stratix® III and other FPGA platforms.
“Altera welcomes PICA200 for FPGA to support our Stratix® FPGA family”, said Nobuo Horiuchi, Director, Japan Marketing, Altera Japan Ltd. “Altera’s Stratix Family and DMP’s graphics solutions for FPGA allow development of highly sophisticated graphics application with advanced design flexibility and will expand the FPGA market much further.”
* Company names and product names described above are either registered trademarks or trademarks of the holders.
Press Release: DMP announces new vector graphics core "SMAPH-F" – Industry’s Highest Performance Vector Graphics IP -
2009.04.23
Digital Media Professionals Inc. (DMP hereafter), the world-class leader of 3D graphics solutions, headquartered in Tokyo Japan today announced the “SMAPH-F”, a next generation vector graphics IP core. DMP will make the core available to customers in 3Q 2009. The core has already been licensed to a major Japanese Tier-1 automotive supplier. DMP will exhibit the SMAPH-F at the “ESEC 2009” (booth#: E38-1 )., one of Japan’s largest embedded technology trade shows, which will be held in Tokyo Japan on May 13th – May 15th.
SMAPH-F enables the industry’s most advanced GUI applications for entry level embedded products such as mobile, TVs, digital cameras, graphics meters, navigation, gaming, office products, etc. at very low cost and low power consumption, while achieving the industry’s best vector graphics performance. SMAPH-F will be compliant with Khronos Group OpenVG 1.1 and provides highly efficient acceleration of vector graphics contents including Adobe® Flash Lite® and SVG. SMAPH-F also supports “DMP Gradient Extension”, a built-in unique hardware acceleration of gradient animations, and additional procedural texturing such as woody pattern. DMP Gradient Extension is provided as an optional feature.
With its support of industry standard OCP and AXI bus interconnect as well as DMP’s state of the art design for optimum system performance with DDR burst accesses, SMAPH-F is a very friendly IP in terms of integration and achievement of performance goals in SoCs which are becoming increasingly complex today.
* Company names and product names described above are either registered trademarks or trademarks of the holders.